Webinar on STA in VLSI Design

Webinar on STA in VLSI Design

A webinar on ‘STA in VLSI Design’ was delivered by one of the M.Tech alumnus -Ms. Shivani Garg, who is currently working as SoC Design Engineer at Intel. It was organized on 18th July 2020 for the VLSI specialization students of B.Tech ECE. Ms. Shivani explained all the concepts of Static Timing Analysis (STA) so thoroughly that students were engrossed in the topic. Towards the end of the webinar, Ms. Shivani also gave tips on how to prepare for placements in VLSI industries. It was really a useful session for students.

Faculty Coordinator: Dr. Vandana Khanna and Ms. Amanpreet Kaur (alumni coordinator)

Student Coordinator: Muneesh

Youtube