DIGITAL SYSTEM DESIGN LABORATORY
This laboratory introduces the student to synthesis and simulation of important digital circuits. Emphasis is on designing and writing different VHDL models (Structural, Dataflow Behavioral modelling) for different Digital circuits. Practical demonstration of the theoretical concepts done in classrooms will enhance the understanding of the students. The experiments included in the curriculum cover majority of the VHDL models of the digital circuits studied in theory. Some additional value added experiments are also included in the end.
The laboratory is well equipped with Xilinx ISE 7.1i tool and CPLD kit ,FPGA kit, Universal Kit etc.
The students are provided with a comprehensive Lab Manual, which is almost self explanatory. All the experiments are well documented with clear circuit diagrams, theory and steps to work with software and kit are clearly explained so that the students are able to perform the experiments with ease and proper understanding.
LIST OF EXPERIMENTS
1. Introduction to Xilinx Software. Design all basic gates (AND, OR,NAND, NOR) using VHDL.
2. Write VHDL programs for the following circuits, check the waveforms and the hardware generated
a. Half adder
b. Full adder
3. Write VHDL programs for the following circuits, check the waveforms and the hardware generated
4. Write VHDL programs for the following circuits,check the waveforms and the hardware generated
5. Write a VHDL program for a code converter and check the waveforms and the hardware generated
6. Write a VHDL program for a FLIP-FLOP and check the wave forms and hardware generated
7. Write a VHDL program for 3-bit counter and check the wave forms and hardware generated
8. Write VHDL programs for the following circuits, check the wave generated a. Register b. Shift register
9. Write a VHDL program for 3-bit parity generator and check hardware generated
10.Write a VHDL program for a combinational circuit using structural style of modeling, check the waveforms and hardware generated.
11. Write a Verilog Program for:
a. Half subtractor
b. Full subtractor
12. Write Verilog program for priority encoder. Check the waveforms
13. Write Verilog program for Master Slave D-Flip flop. Check the waveforms
Value Added Experiments:
15. Traffic light controller using VHDL
16.Implement any three (given above) on FPGA/CPLD kit.